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STM8S bảng dữ liệu(PDF) 238 Page - STMicroelectronics |
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STM8S bảng dữ liệu(HTML) 238 Page - STMicroelectronics |
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238 / 467 page ![]() 16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 238/467 DocID14587 Rev 14 Channel configured in input 7 654 3210 IC1F[3:0] IC1PSC[1:0] CC1S[1:0] rw rw rw rw rw rw rw rw Bits 7:4 IC1F[3:0]: Input capture 1 filter This bitfield defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fMASTER 0001: fSAMPLING= fMASTER, N = 2 0010: fSAMPLING= fMASTER, N = 4 0011: fSAMPLING= fMASTER, N = 8 0100: fSAMPLING= fMASTER/2, N = 6 0101: fSAMPLING= fMASTER/2, N = 8 0110: fSAMPLING= fMASTER/4, N = 6 0111: fSAMPLING= fMASTER/4, N = 8 1000: fSAMPLING= fMASTER/8, N = 6 1001: fSAMPLING= fMASTER/8, N = 8 1010: fSAMPLING= fMASTER/16, N = 5 1011: fSAMPLING= fMASTER/16, N = 6 1100: fSAMPLING= fMASTER/16, N = 8 1101: fSAMPLING= fMASTER/32, N = 5 1110: fSAMPLING= fMASTER/32, N = 6 1111: fSAMPLING= fMASTER/32, N = 8 Bits 3:2 IC1PSC[1:0]: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E = 0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: Capture is done once every 2 events 10: Capture is done once every 4 events 11: Capture is done once every 8 events Note: The internal event counter is not reset when IC1PSC is changed on the fly. In this case the old value is used until the next capture occurs. To force a new value to be taken in account immediately, the CC1E bit can be cleared and set again. Bits 1:0 CC1S[1:0]: Capture/compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1FP1 10: CC1 channel is configured as input, IC1 is mapped on TI2FP1 11: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER1 and updated). |
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