DP83261AVF datasheet(46/132 Pages) NSC

46 / 132 page

60 Control Information (Continued)

Internal Event Latch Register (IELR)

The Internal Event Latch Register (IELR) reports internal errors in the BMAC device These errors include MAC Parity errors and

inconsistencies in the Receiver and Transmitter state machines

After an internal state machine is detected and reported (bit RSMERR for the receiver and TSMERR for the transmitter) the

Current Receive Status Register (CRS0) and Current Transmit Status Register (CTS0) continue to be updated as normal

Errors internal to the BMAC device cause a MAC

Reset

ACCESS RULES

Address

Read

Write

28h

Always

Condition

RES

TSMERR

RSMERR

RES

MPE

Bit

Symbol

Description

MPE

MAC Interface Parity Error

Indicates a Parity Error on the MAC Request Data pins (MRD7 – 0) when

parity is enabled on the MA

Request Interface (bits MRP of the Mode Register is set and pin TXACK is

asserted)

RES

Reserved

RSMERR

Receive State Machine Error

Indicates inconsistency in the Receiver state machine When set causes

bit MCRST of the Function Register to be set

TSMERR

Transmit State Machine Error

Indicates inconsistency in the Transmitter state machine When set

causes bit MCRST of the Function Register to be set

D4 – 7

RES

Reserved

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