AX68004LF datasheet(23/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

2.0 Function Description

2.1 Clock Generation

AX6800x requires an external 12MHz crystal as the main clock source. The clock source provides the reference

timing to the internal 96MHz PLL (Phase-Locked Loop) block to generate 96MHz clock. The 96MHz clock can be

divided to 48 and 12MHz clock. The SYSCK_SEL input is used to select the operating system clock frequency

between 48MHz and 96MHz. The 12MHz and 48MHz can be used as the clock source for the USB process to

handle the data transmission and some USB protocol scheme. The recommended reference frequency of external

12MHz Crystal is 12MHz +/-50ppm, 45 ~ 55% clock duty cycle.

2.2 Reset Generation

During the VDDIO power-on, the internal Power-On-Reset (POR) can generate a reset pulse to reset all the

function blocks, including Flash memory, CPU Core and all the peripherals, when the VDDIO power pin rises to

certain threshold voltage level. The RST_N input is “AND” operating with the POR output so the manual reset

event can be applied by external system circuitry.

NOTICE: Due to AX6800x needs to be supplied dual powers for all IO and core powers and the POR is designed

to detect the VDDIO power only. It is important to make sure the VDDK stabled before VDDIO ramp up or down

cross the Vrr and Vfr voltages. Suggested the VDDIO and VDDK are from same power source and use LDO

regulator for 1.8V power source (Drop Out voltage ≤ 0.3 V) on the board level design. Please reference Section 4.3

and 4.4 for the detail.

AX68004LF bảng dữ liệu(PDF) 23 Page - ASIX Electronics Corporation