AT90LS8535-4PI datasheet(44/127 Pages) ATMEL

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AT90S/LS8535

1041H–11/01

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,

0, 0, 0, 0, 0, 0 | 1, 1, 1,...

In PWM mode, this bit has no effect.

• Bits 2, 1, 0 – CS22, CS21, CS20: Clock Select Bits 2, 1 and 0

The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter2.

The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes

are scaled directly from the CK oscillator clock.

Timer/Counter2 – TCNT2

This 8-bit register contains the value of Timer/Counter2.

Timer/Counter2 is realized as an up or up/down (in PWM mode) counter with read and

write access. If the Timer/Counter2 is written to and a clock source is selected, it contin-

ues counting in the timer clock cycle following the write operation.

Timer/Counter2 Output

Compare Register – OCR2

The Output Compare Register is an 8-bit read/write register.

The Timer/Counter Output Compare Register contains the data to be continuously com-

pared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A

compare match only occurs if Timer/Counter2 counts to the OCR2 value. A software

write that sets TCNT2 and OCR2 to the same value does not generate a compare

match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the

compare event.

Table 18. Timer/Counter2 Prescale Select

CS22

CS21

CS20

Description

Timer/Counter2 is stopped.

PCK2

PCK2/ 8

PCK2/ 32

PCK2/ 64

PCK2/128

PCK2/256

PCK2/1024

Bit

765

4321

$24 ($44)

MSB

LSB

TCNT2

Read/Write

R/W

Initial Value

000

0000

Bit

765

4321

$23 ($43)

MSB

LSB

OCR2

Read/Write

R/W

Initial Value

000

0000

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