MPC852TZT50 datasheet(56/80 Pages) FREESCALE

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MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

FEC Electrical Characteristics

Figure 57. SPI Slave (CP = 1) Timing Diagram

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing

specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII

signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV,

MII_RX_ER, MII_RX_CLK)

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum

frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%.

Table 25 provides information on the MII receive signal timing.

Table 25. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup

—

MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold

—

MII_RX_CLK pulse width high

35%

65%

MII_RX_CLK period

MII_RX_CLK pulse width low

35%

65%

MII_RX_CLK period

SPIMOSI

(Input)

SPICLK

(CI=0)

(Input)

SPICLK

(CI=1)

(Input)

SPIMISO

(Output)

180

Data

181

182

msb

lsb

181

177

182

175

179

SPISEL

(Input)

174

Data

msb

lsb

Undef

178

176

182

msb

172

173

171

170

181

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