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MPC852TZT50 bảng dữ liệu(PDF) 51 Page - Freescale Semiconductor, Inc

tên linh kiện MPC852TZT50
Giải thích chi tiết về linh kiện  Hardware Specifications
PDF  80 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC852TZT50 bảng dữ liệu(HTML) 51 Page - Freescale Semiconductor, Inc

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MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconductor
51
CPM Electrical Characteristics
Figure 49. Ethernet Collision Timing Diagram
Figure 50. Ethernet Receive Timing Diagram
134
TENA inactive delay (from TCLK3 rising edge)
10
50
ns
135
RSTRT active delay (from TCLK3 falling edge)
10
50
ns
136
RSTRT inactive delay (from TCLK3 falling edge)
10
50
ns
137
REJECT width low
1
—
CLK
138
CLKO1 low to SDACK asserted 2
—
20
ns
139
CLKO1 low to SDACK negated 2
—
20
ns
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 22. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124
123
127
126
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