CS61880 datasheet(37/70 Pages) CIRRUS

37 / 70 page

CS61880

DS450PP3

14.14 LOS/AIS Mode Enable Register (0Dh)

14.15 Automatic TAOS Register (0Eh)

14.16 Global Control Register (0Fh)

BIT

NAME

Description

[7:0]

LAME 7-0 Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; setting bit n to “0”

enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after

power-up or reset.

BIT

NAME

Description

[7:0]

ATAO 7-0

Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected.

BIT

NAME

Description

This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,

encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for

all eight channels. Register bits default to 00h after power-up or reset.

[7]

AWG Auto-

Increment

The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address

the phase samples address portion of the address register increments after each read or

write access. This bit must be set before any bit in the AWG Enable register is set, if this

function is required.

[6]

RAISEN

On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.

0 = Disabled

1 = Enabled

[5]

RSVD

RESERVED (This bit must be set to 0.)

[4]

CODEN

Line encoding/decoding Selection

0 = HDB3

1 = AMI

[3]

FIFO

LENGTH

Jitter Attenuator FIFO length Selection

0 = 32 bits

1 = 64 bits

[2]

JACF

Jitter Attenuator Corner Frequency Selection

0 = 1.25 Hz

1 = 2.50 Hz

[1:0]

JASEL [1:0]

These bits select the position of the Jitter Attenuator.

Table 11. Jitter Attenuator Position Selection

JASEL 1

JASEL 0

POSITION

Disabled

Transmit Path

Disabled

Receive Path

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