CS61880 datasheet(55/70 Pages) CIRRUS

55 / 70 page

CS61880

DS450PP3

19.5 Receiver Analog Characteristics

(TA = -40

° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V))

Notes: 10. Parameters guaranteed by design and characterization.

11. Using components on the CDB61880 evaluation board in Internal Match Impedance Mode.

12. Return loss = 20log10 ABS((Z1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver,

and Z0 = cable impedance.

13. Assuming that jitter free clock is input to TCLK.

14. Jitter tolerance for 6 dB input signal levels. Jitter tolerance increases at lower frequencies. HDB3 coders

enabled.

15. In Data Recovery Mode.

16. Jitter Attenuator in the receive path.

Parameter

Min.

Typ

Max

Units

Allowable Cable Attenuation @ 1024 kHz

- 12

RTIP/RRING Input Impedance

E1 120

Ω Load

(Internal Line matching mode)

E1 75

Ω Load

Note 10

13k

Ω

RTIP/RRING Input Impedance

E1 120

Ω Load

(External Line matching mode)

E1 75

Ω Load

Note 10

13k

Ω

Receiver Dynamic Range

0.5

Signal to Noise margin (Per G.703, O151 @ 6 dB cable Atten).

-18

Receiver Squelch Level

150

LOS Threshold

200

LOS Hysteresis

Data Decision Threshold

Note 10

% of

peak

Input Jitter Tolerance

1 Hz - 1.8 Hz

Notes 10, 14, 16

20 Hz - 2.4 kHz

18 kHz - 100 kHz

1.5

0.2

Input Return Loss

51 kHz - 102 kHz

102 kHz - 2048 kHz

Notes 10, 11, 12

2048 kHz - 3072 kHz

-18

-28

-30

-27

CS61880 bảng dữ liệu(PDF) 55 Page - Cirrus Logic

CS61880 bảng dữ liệu(HTML) 55 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL