CS61880 datasheet(12/70 Pages) CIRRUS

12 / 70 page

CS61880

DS450PP3

WR/DS/SDI

J14

Write Enable/Data Strobe/Serial Data

Intel Parallel Host Mode - This pin, “WR”, functions as

a write enable.

Motorola Parallel Host Mode - This pin, “DS“, functions as

a data strobe input.

Serial Host Mode - This pin, “SDI”, functions as the serial

data input.

Hardware Mode - This pin is not used and should be con-

nected to ground.

RD/RW

J13

Read Enable/Read/Write

Intel Parallel Host Mode - This pin, “RD”, functions as a

read enable.

Motorola Parallel Host Mode - This pin, “R/W”, functions

as the read/write input signal.

Hardware Mode - This pin is not used and should be con-

nected to ground.

ALE/AS/SCLK

J12

Address Latch Enable/Address Strobe/Serial Clock

Intel Parallel Host Mode - This pin, “ALE”, functions as the

Address Latch Enable when configured for multiplexed ad-

dress/data operation.

Motorola Parallel Host Mode - This pin, “AS”, functions as

the active “low” address strobe when configured for multi-

plexed address/data operation.

Serial Host Mode - This pin, “SCLK”, is the serial clock

used for data I/O on SDI and SDO.

Hardware Mode - This pin is not used and should be con-

nected to ground.

CS/JASEL

J11

Chip Select Input/Jitter Attenuator Select

Host Mode - This active low input is used to enable ac-

cesses to the microprocessor interface in either serial or

parallel mode.

Hardware Mode - This pin controls the position of the Jitter

Attenuator.

SYMBOL

LQFP

FBGA

TYPE

DESCRIPTION

Table 3. Jitter Attenuation Selection

Pin State

Jitter Attenuation Position

LOW

Transmit Path

HIGH

Receive Path

OPEN

Disabled

CS61880 bảng dữ liệu(PDF) 12 Page - Cirrus Logic

CS61880 bảng dữ liệu(HTML) 12 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL