SSD1926QL9 datasheet(33/47 Pages) ETC2

33 / 47 page

SSD1926

Rev 1.2

P 33/47

Dec 2007

Solomon Systech

Table 10-3 : Generic #1 Interface Timing

Symbol

Parameter

Min

Max

Units

CLK

Bus Clock frequency

MHz

CLK

Bus Clock period

1/f

CLK

Clock pulse width high

Clock pulse width low

A[18:1], M/R# setup to first CLK rising edge where CS# = 0 and

either RD0#, RD1# = 0 or WE0#, WE1# = 0

A[18:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# rising

edge

CS# setup to CLK rising edge

CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge

t7a

RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK

TCLK

t7b

RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK

÷2

TCLK

t7c

RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK

÷3

TCLK

t7d

RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK

÷4

TCLK

RD0#, RD1#, WE0#, WE1# setup to CLK rising edge

Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#

driven low

t10

Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#

high impedance

t11

D[15:0] setup to third CLK rising edge where CS# = 0 and

WE0#,WE1#=0 (write cycle)(see note 1)

t12

D[15:0] hold from WAIT# rising edge (write cycle)

t13

RD0#, RD1# falling edge to D[15:0] driven (read cycle)

t14

WAIT# rising edge to D[15:0] valid (read cycle)

t15

RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)

1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.

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