SSD1926QL9 datasheet(20/47 Pages) ETC2

tên linh kiện	SSD1926QL9

Giải thích chi tiết về linh kiện	JPEG Coder SD interface 256K Embedded Display SRAM Image Processor CMOS

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20 / 47 page

Solomon Systech

Dec 2007 P 20/47

Rev 1.2

SSD1926

FUNCTIONAL BLOCK DESCRIPTIONS

7.1

Phase Lock Loop (PLL)

The built-in PLL synthesize the internal clock by an external 2MHz – 4MHz clock through the CLKI and CLKO.

RC circuit should be connected if internal PLL is selected. The input of clock source can be either oscillator or

crystal. If oscillator is used, the clock source is input directly to CLKI and leave CLKO floating. The target

maximum output frequency of the PLL is 85MHz. If sync MCU interface, PLL should be disabled and use direct

clock input to CLKI2.

10kohm

6.4nF

250pF

PLL_VCTRL

10Mohm

2-4MHz

CLKI

CLKO

15pF

If oscillator input directly to CLKI, this circuit can be omitted

RC circuit for PLL_VCTRL

Figure 7-1 : Circuit for PLL enable

7.2

Embedded Memory

The 256kByte embedded memory can be access by the modules for different functions. For example, frame

buffer, SD read/write buffer, internal buffer for JPEG encoding/decoding, encoded JPEG image output and so

on.

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