ARM926EJ datasheet(39/236 Pages) ETC2

39 / 236 page

Programmer’s Model

ARM DDI 0198E

2-9

S bit

Specifies if the cache is a unified cache, S=0, or separate ICache and

DCache, S=1. If S=0, the Isize and Dsize fields both describe the unified

cache and must be identical. In the ARM926EJ-S processor, this bit is set

to a 1 to denote separate caches.

Dsize

Specifies the size, line length, and associativity of the DCache, or of the

unified cache if the S bit is 0.

Isize

Specifies the size, length, and associativity of the ICache, or of the

unified cache if the S bit is 0.

The Ctype field specifies if the cache supports lockdown or not, and how it is cleaned.

The encoding is shown in Table 2-6. All unused values are reserved.

The Dsize and Isize fields in the Cache Type Register have the same format. This is

shown in Figure 2-3.

Figure 2-3 Dsize and Isize field format

Size

The Size field determines the cache size in conjunction with the M bit.

Assoc

The Assoc field determines the cache associativity in conjunction with

the M bit.

M bit

The multiplier bit determines the cache size and cache associativity

values in conjunction with the Size and Assoc fields. If the cache is

present, M must be set to 0. If the cache is absent, M must be set to 1. For

the ARM926EJ-S processor, M is always set to 0.

Len

The Len field determines the line length of the cache.

Table 2-6 Ctype encoding

Value

Method

Cache cleaning

Cache lockdown

b1110

Write-back

Format Ca

a. See Cache Lockdown Register c9 on page 2-25 for more details on

Format C for cache lockdown.

11 10 9

6 5

3 2 1 0

0 0

Size

Assoc

M Len

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