ARM926EJ datasheet(21/236 Pages) ETC2

21 / 236 page

Preface

ARM DDI 0198E

xxi

Key to timing diagram conventions

Single-bit signals are sometimes shown as HIGH and LOW at the same time and they

look similar to the bus change shown in Key to timing diagram conventions. If a

single-bit signal is shown like this then its value does not affect the accompanying

description.

Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is

active-HIGH or active-LOW. Asserted means:

•

HIGH for active-HIGH signals

•

LOW for active-LOW signals.

Lower-case n

At the start or end of a signal name denotes an active-LOW signal.

Prefix A

Denotes global Advanced eXtensible Interface (AXI) signals.

Prefix AR

Denotes AXI read address channel signals.

Prefix AW

Denotes AXI write address channel signals.

Prefix B

Denotes AXI write response channel signals.

Prefix C

Denotes AXI low-power interface signals.

Prefix H

Denotes Advanced High-performance Bus (AHB) signals.

Prefix P

Denotes Advanced Peripheral Bus (APB) signals.

Prefix R

Denotes AXI read data channel signals.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

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