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ARM926EJ bảng dữ liệu(PDF) 92 Page - List of Unclassifed Manufacturers |
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ARM926EJ bảng dữ liệu(HTML) 92 Page - List of Unclassifed Manufacturers |
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92 / 236 page ![]() Memory Management Unit 3-28 Copyright © 2001-2008 ARM Limited. All rights reserved. ARM DDI 0198E 3.6 External aborts In addition to the MMU generated aborts, external aborts can be generated for certain types of access that involve transfers over the AHB bus. These can be used to flag errors on external memory accesses. However, not all accesses can be aborted in this way. The following accesses can be externally aborted: • page walks • noncached reads • nonbuffered writes • noncached read-lock-write (SWP) sequence. For a read-lock-write (SWP) sequence, if the read externally aborts, the write is always attempted. A swap to an NCB region is forced to have precisely the same behavior as a swap to an NCNB region. This means that the write part of a swap to an NCB region can be externally aborted. 3.6.1 Enabling the MMU Before enabling the MMU using CP15 c1 you must: 1. Program the TTB register (CP15 c2) and the domain access control register (CP15 c3). 2. Program first-level and second-level page tables as required, ensuring that a valid translation table is placed in memory at the location specified by the TTB register. When these steps have been performed, you can enable the MMU by setting CP15 c1 bit 0 HIGH. Care must be taken if the translated address differs from the untranslated address because several instructions following the enabling of the MMU might have been prefetched with the MMU off (VA = MVA = PA). In this case, enabling the MMU can be considered as a branch with delayed execution. A similar situation occurs when the MMU is disabled. Consider the following code sequence: MRC p15, 0, R1, c1, C0, 0 ; Read control register ORR R1, #0x1 ; Set M bit MCR p15, 0,R1,C1, C0,0 ; Write control register and enable MMU Fetch Flat Fetch Flat Fetch Translated |
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