TMS320DM643 datasheet(79/160 Pages) TI

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5.7

Clock PLL

5.7.1

Clock PLL Device-Specific Information

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

The PLL controller features hardware-configurable PLL multiplier controller, dividers (/2, /4, /6, and /8),

and reset controller. The PLL controller accepts an input clock, as determined by the logic state on the

CLKMODE[1:0] pins, from the CLKIN pin. The resulting clock outputs are passed to the DSP core,

peripherals, and other modules inside the C6000™ DSP.

Most of the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This

source clock either drives the PLL, which multiplies the source clock frequency to generate the internal

CPU clock, or bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed.

Figure 5-10 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.

To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and

the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For

the input clock timing requirements, see the input and output clocks electricals section.

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the DSP requirements in this data sheet (see the electrical characteristics over

recommended ranges of supply voltage and operating case temperature table and the input and output

clocks electricals section).

DM643 Peripheral Information and Electrical Specifications

TMS320DM643 bảng dữ liệu(PDF) 79 Page - Texas Instruments