TMS320DM643 datasheet(54/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register

(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register

determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked

(LOCKSTAT bit = 0), see Figure 3-4. A peripheral can only be enabled when the PERCFG register is

"unlocked" (LOCKSTAT bit = 0).

Read Accesses

Reserved

LOCKSTAT

R-0

R-1

Write Accesses

LOCK

W-0

Legend: R = Read only, R/W = Read/Write, -n = value after reset

Figure 3-4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] - Read/Write Accesses

Table 3-5. PCFGLOCK Register Selection Bit Descriptions - Read Accesses

BIT

NAME

DESCRIPTION

31:1

Reserved

Reserved. Read-only, writes have no effect.

Lock status bit.

Determines whether the PERCFG register is locked or unlocked.

LOCKSTAT

0 = Unlocked, read accesses to the PERCFG register allowed.

1 = Locked, write accesses to the PERCFG register do not modify the register state [default].

Reads are unaffected by Lock Status.

Table 3-6. PCFGLOCK Register Selection Bit Descriptions - Write Accesses

BIT

NAME

DESCRIPTION

Lock bits.

31:0

LOCK

0x10C0010C = Unlocks PERCFG register accesses.

Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary

overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the

PERCFG register with the necessary enable bits set.

Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation

between the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the

PERCFG register after the write is issued forces the CPU to wait for the write to the PERCFG register to

occur.

Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128

CPU cycles before accessing the enabled peripheral. The user must ensure that no accesses are

performed to a peripheral while it is disabled.

Device Configurations

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