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Giải thích chi tiết về linh kiện  2.5V Uniform Sector Dual and Quad Serial Flash
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2.5V Uniform Sector
Dual and Quad Serial Flash
GD25VQ64C
21
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched
in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0.
The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of
Status Register (S9) must be set to enable for the Quad Output Fast Read command.
Figure 10. Quad Output Fast Read Sequence Diagram
Command
0
1
2
3
4
5
6
7
6BH
CS#
SCLK
SI(IO0)
SO(IO1)
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
34 35 36 37
33
1
5
1
5
1
5
1
38 39
Byte1
32
42 43 44 45
41
46 47
40
5
Dummy Clocks
0
4
0
4
0
4
0
4
4
5
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
CS#
SCLK
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
2
6
2
6
2
6
2
6
6
3
7
3
7
3
7
3
7
7
Byte2 Byte3 Byte4



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