PCD6003 datasheet(55/96 Pages) PHILIPS

55 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6003

2. Writing MAGP/P2GP is independent of the setting of the P4.3 SFR bit if P4CFG.5 (EAM) is set to logic 1, otherwise

(EAM logic 0) P4.3 must be logic 1.

3. The WR/RD pins are always active when doing a MOVX. They can be turned inactive for MOVX below 200H by

setting the ARD bit in PCON in case the EAM Bit is set to logic 1.

4. P0/P2 are standard 80C51 ports. An external latch is not needed since the demultiplexing of P0 is taken over by the

MA port.

5. The MA/P2/ConfReg registers are part of the auxiliary RAM address space and can be disabled by setting the ARD

bit in PCON in case the EAM Bit is set to logic 1.

Table 48 External memory control registers

Table 49 Conﬁguration Register (ConfReg); reset state 00H

12.1

Supported ﬂash memories

Table 50 shows the ports that are available in an application using various flash memories.

For all types of flash memory shown in Table 50 (except for the parallel flash memory) at least 34 general purpose

I/O pins can be used for the application (display, line interface, keypad and LEDs; for example). P0 can also be used for

the application to connect memory mapped peripherals such as an LCD controller or keypad. P0 pins have no output

latch, so data written to this port will not remain here.

There are many different types of flash memories manufactured, and the PCD6003 will work with many of them. Table 51

explains the most important characteristics of a few of the commercially available flash memories which can be

connected to the PCD6003 directly.

Table 50 Ports available for the application

Note

1. P0 can be used as a data bus for other peripherals if not conflicting with the flash memory.

EXTERNAL MEMORY CONTROL

REGISTERS

ADDRESS P2/P0

(P4.3 = 1, EAM = 0

or ARD = 0, EAM = 1, EA=1)

RESET VALUE

ACCESS

ConfReg

0200H

00H

R and W

0201H

00H

R and W

0202H

00H

R and W

76543210

−−−

P2GP

MAGP

−−−

FLASH

MEMORY

PORTS USED BY FLASH

PORTS AVAILABLE FOR APPLICATION

I/O

CAD

−

P4.1, P4.2 and P4.3

P1, P3, P4.0,

P4.4 and P4.5

P0(1)

MA and P2

SPI/Microwire

−

P4.4

P4.1, P4.2 and P4.3

P1, P3,

P4.0 and P4.5

MA and P2

I2C-bus

P1.6 and P1.7

−−

P1, P3 and P4

(except P4.3)

P0(1)

MA, P2 and P4.3

Parallel

−

MA, P2, P4.0, P4.1,

P4.2 and P4.3

P1, P3,

P4.4 and P4.5

P0(1)

−

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