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SC4525EEVB bảng dữ liệu(PDF) 17 Page - Semtech Corporation

tên linh kiện SC4525EEVB
Giải thích chi tiết về linh kiện  28V 3A Step-Down Switching Regulator
PDF  23 Pages
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nhà sản xuất  SEMTECH [Semtech Corporation]
Trang chủ  http://www.semtech.com
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SC4525E
7
Applications Information (Cont.)
Thermal Considerations
For the power transistor inside the SC4525E, the
conduction loss P
C, the switching loss PSW, and bootstrap
circuit loss P
BST, can be estimated as follows:
O
CESAT
C
I
V
D
P
×
×
=
SW
O
IN
S
SW
F
I
V
t
2
1
P
×
×
×
×
=
40
I
V
D
P
O
BST
BST
×
×
=
whereV
BST is the BST supply voltage and tS is the equivalent
switching time of the NPN transistor (see Table 4).
Table 4. Typical switching time
1A
2A
3A
12V
12.5ns
15.3ns
18ns
24V
22ns
25ns
28ns
28V
25.3ns
28ns
31ns
Load Current
Input Voltage
In addition, the quiescent current loss is
2mA
V
P
IN
Q
×
=
The total power loss of the SC4525E is therefore
Q
BST
SW
C
TOTAL
P
P
P
P
P
=
+
+
=
The temperature rise of the SC4525E is the product of the
total power dissipation (see previous equation) and q
JA
(36oC/W), which is the thermal impedance from junction
to ambient for the SOIC-8 EDP package.
It is not recommended to operate the SC4525E above
25oC junction temperature.
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse currents (Figure 0). For jitter-free
operation,thesizeoftheloopformedbythesecomponents
should be minimized. Since the power switch is already
integrated within the SC4525E, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using large vias directly under the device.
IN
V
O UT
V
L
Z
Figure 10 — Pulse Current Loop
NOTE: Heavy lines indicate the critical pulse current loop. The stray
inductance of this loop should be minimized.



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