SC4525EEVB datasheet(15/23 Pages) SEMTECH

15 / 23 page

SC4525E

Applications Information (Cont.)

Minimum Soft-start Capacitance Css

To ensure normal operation, the minimum soft-start

capacitance C

SS can be calculated in terms of the output

capacitance C

O and output load current IO according to

the following equations.

Substituting the first equation into the second equation,

where V

SS is the soft-start capacitor voltage and ISS is the

soft-start charging current. V

is the voltage defined in

Figure 2.

To ensure successful startup, the total current drawn

from the output must be less than the maximum output

capability of the part,

3.5A

≤

Substituting the third equation of this section into the

previous equation,

3.5A

≤

Rearranging,













−

≥

3.5A

SS(MAX)

Therefore the minimum C

SS depends on the output

capacitance and the load current. Larger C

SS is necessary

when starting into a heavy load (small R).

If the regulator is to be started by turning on a bench

power supply then C

SS will be best determined empirically

because the rise time of a power supply can range from

a few milliseconds to a few hundred milliseconds. With

the maximum load applied, the output voltage rise is

observed using a 22nF for C

SS. Adjust CSS until a linear VOUT

ramp is achieved.

Loop Compensation

The goal of compensation is to shape the frequency

response of the converter so as to achieve high DC

accuracy and fast transient response while maintaining

loop stability (see Figure 8).

The block diagram in Figure 8 shows the control loops of a

buck converter with the SC4525E. The inner loop (current

loop) consists of a current sensing resistor (R

s=3.53mW)

and a current amplifier (CA) with gain (G

CA=8.5). The

outer loop (voltage loop) consists of an error amplifier

(EA), a PWM modulator, and a LC filter.

Since the current loop is internally closed, the remaining

task for the loop compensation is to design the voltage

compensator (C

5, R7, and C8).

C o

R esr

C O M P

R EF

C O N TR O LLER AN D SC H O TTKY D IO D E

PW M

M O D U LATO R

Vram p

C A

C 5

R 7

C 8

R s

Figure 8. Block diagram of control loops

For a converter with switching frequency F

SW, output

inductance L

, output capacitance CO and loading R, the

control (V

C) to output (VO) transfer function in Figure 8 is

given by:

)

/ω

s/ω

)

s/ω

)

ESR

PWM

This transfer function has a finite DC gain

PWM

≈

It has an ESR zero F

Z at

ESR

ω =

(

)

[

]

1.2V

−

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