SC4525EEVB datasheet(16/23 Pages) SEMTECH

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SC4525E

Applications Information (Cont.)

It has a dominant low-frequency pole F

P at

and double poles at half the switching frequency.

Including the voltage divider (R

4 and R6), the control to

feedback transfer function is found and plotted in Figure

9 as the converter gain.

Since the converter gain has only one dominant pole at

low frequency, a simple Type-2 compensation network

is sufficient for voltage loop compensation. As shown in

Figure 9, the voltage compensator has a low frequency

integrator pole, a zero at F

Z, and a high frequency pole

at F

P. The integrator is used to boost the gain at low

frequency. The zero is introduced to compensate the

excessive phase lag at the loop gain crossover due to the

integrator pole (-90deg) and the dominant pole (-90deg).

The high frequency pole nulls the ESR zero and attenuates

high frequency noise.

Fsw/2

Fz1

Fp1

10K

100K

10M

-60

-30

FREQUENCY (Hz)

CONV

ERTER

GAIN

LOOP

GAIN

COMP

ENSAT

OR GA

Figure 9 — Bode plots for voltage loop design

Therefore, the procedure of the voltage loop design for

the SC4525E can be summarized as:

() Plot the converter gain, i.e. control to feedback transfer

function.

(2) Select the open loop crossover frequency, F

C, between

0% and 20% of the switching frequency. At F

C, find the

required compensator gain, A

C. In typical applications with

ceramic output capacitors, the ESR zero is neglected and

the required compensator gain at F

C can be estimated by

(3) Place the compensator zero, F

Z, between 0% and

20% of the crossover frequency, F

(4) Use the compensator pole, F

P, to cancel the ESR zero, FZ.

(5) Then, the parameters of the compensation network

can be calculated by

C =

where g

m=0.3mA/V is the EA gain of the SC4525E.

Example: Determine the voltage compensator for an

800kHz, 2V to 3.3V/3A converter with 47uF ceramic

output capacitor.

Choose a loop gain crossover frequency of 80kHz, and

place voltage compensator zero and pole at F

Z=6kHz

(20% of F

C), and FP=600kHz. From the equation in step

(2), the required compensator gain at F

C is

14.1

18.5

log

Then the compensator parameters are

16.9k

14.1

−

0.589nF

16.9

2π

15.7pF

600

Select R

7=6.9k, C5=0.68nF, and C8=22pF for the design.

Compensator parameters for various typical applications

are listed in Table 5.

ω ≈

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