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74LVC1G74DP bảng dữ liệu(PDF) 9 Page - NXP Semiconductors

tên linh kiện 74LVC1G74DP
Giải thích chi tiết về linh kiện  Single D-type flip-flop with set and reset; positive edge trigger
PDF  19 Pages
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nhà sản xuất  PHILIPS [NXP Semiconductors]
Trang chủ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC1G74DP bảng dữ liệu(HTML) 9 Page - NXP Semiconductors

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2005 Feb 01
9
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
AC CHARACTERISTICS
GND = 0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH
propagation delay CP to Q, Q
see Figs 6 and 8 1.65 to 1.95
1.5
6.0
13.4
ns
2.3 to 2.7
1.0
3.5
7.1
ns
2.7
1.0
3.5
7.1
ns
3.0 to 3.6
1.0
3.5(2)
5.9
ns
4.5 to 5.5
1.0
2.5
4.1
ns
propagation delay SD to Q, Q
see Figs 7 and 8 1.65 to 1.95
1.5
6.0
12.9
ns
2.3 to 2.7
1.0
3.5
7.0
ns
2.7
1.0
3.5
7.0
ns
3.0 to 3.6
1.0
3.0(2)
5.9
ns
4.5 to 5.5
1.0
2.5
4.1
ns
propagation delay RD to Q, Q
see Figs 7 and 8 1.65 to 1.95
1.5
5.0
12.9
ns
2.3 to 2.7
1.0
3.5
7.0
ns
2.7
1.0
3.5
7.0
ns
3.0 to 3.6
1.0
3.0(2)
5.9
ns
4.5 to 5.5
1.0
2.5
4.1
ns
tW
clock pulse width HIGH or LOW
see Figs 6 and 8 1.65 to 1.95
6.2
−−
ns
2.3 to 2.7
2.7
−−
ns
2.7
2.7
−−
ns
3.0 to 3.6
2.7
1.3(2)
−
ns
4.5 to 5.5
2.0
−−
ns
set or reset pulse width LOW
see Figs 7 and 8 1.65 to 1.95
6.2
−−
ns
2.3 to 2.7
2.7
−−
ns
2.7
2.7
−−
ns
3.0 to 3.6
2.7
1.6(2)
−
ns
4.5 to 5.5
2.0
−−
ns
trem
removal time set or reset
see Figs 7 and 8 1.65 to 1.95
1.9
−−
ns
2.3 to 2.7
1.4
−−
ns
2.7
1.3
−−
ns
3.0 to 3.6
1.2
−3.0(2) −
ns
4.5 to 5.5
1.0
−−
ns
tsu
set-up time D to CP
see Figs 6 and 8 1.65 to 1.95
2.9
−−
ns
2.3 to 2.7
1.7
−−
ns
2.7
1.7
−−
ns
3.0 to 3.6
1.3
0.5(2)
−
ns
4.5 to 5.5
1.1
−−
ns



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