MPC866P datasheet(15/92 Pages) FREESCALE

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MOTOROLA

MPC866/859 Hardware Speciﬁcations

Layout Practices

These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic

discharge (ESD) protection diodes are forward-biased and excessive current can ﬂow through these diodes.

If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 4

can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential

difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate

the maximum potential difference on powerdown.

Figure 4. Example Voltage Sequencing Circuit

Layout Practices

Each VDD pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply.

Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply

pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at

least four 0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board

designed should be characterized and additional appropriate decoupling capacitors should be used if

required. The capacitor leads and associated printed-circuit traces connecting to chip VDD and GND should

be kept to less than 1/2” per capacitor lead. At a minimum, a four-layer board employing two inner layers

as VDD and GND planes should be used.

All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection

length should be minimized in order to minimize undershoot and reﬂections caused by these fast output

switching times. This recommendation particularly applies to the address and data buses. Maximum PC

trace lengths of 6” are recommended. Capacitance calculations should consider all device loads as well as

parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient

currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,

please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the MPC866

User’s Manual.

Bus Signal Timing

The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated

in half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be conﬁgured for a 50-MHz

bus). Table 7 and Table 8 show the frequency ranges for standard part frequencies.

VDDH

VDDL

1N5820

MUR420

Freescale Semiconductor, Inc.

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