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¡ Semiconductor

MSM7580

In this device, internal operating signals are generated according to the ADPCM side SYNC

(SYNCA) signal.

The timings are shouwn in the figures (a) and (b);

The arithmetic operation of CODER is performed at "A" in the figure (a).

The arithmetic operation of DECODER is performed at "B" in the figure (b).

Therefore, when the conversion delay time Tsip of the CODER is less than t1, ADPCM is output

at the timing of Tsoa.

When Tsip is more than t1, ADPCM is output at the timing of Tsoa + 125ms.

For DECODER, when Tsia<t3 and Tsop<t2, the conversion delay time is Tsop-Tsia.

As mentioned above, a data ship may occur at Tsip=t1 in CODER, and at Tsia=t3 and Tsop=t2

in DECODER.

Therefore, the timings of SYNC signals of both PCM and ADPCM sides should not be set up in

the range about

±500nsec of Tsip=t1, Tsia=t3 and Tsop=t2.

For normal operation, SYNC clocks for ADPCM and PCM sides should be continuous at 8 kHz

and synchronized with each other even if their phases are different.