14/17

¡ Semiconductor

MSM7580

NOTES ON USAGE

(1) Through Mode (CODER Side)

BCLK

PCM side SYNC (SYNCP)

PCM Input (SIP)

Internal Latch Timing

ADPCM side SYNC (SYNCA)

ADPCM side SYNC (SYNCA)

Through-Data Output (SOA)

Through-Data Output (SOA)

t0

t1

12345678

PCMDATA1

ADPCMDATA0

ADPCMDATA1

ADPCMDATA2

PCMDATA2

PCMDATA3

ADPCMDATA0

ADPCMDATA1

*t1 is the falling edge of the 8th BCLK counted from t0.

(A) When SYNCA rises after t1, PCMDATA1 is output to ADPCMDATA1.

(B) When SYNCA rises before t1, PCMDATA1 is output to ADPCMDATA1.

If SYNCA rises near the t1 and jitter occurs, data slip may occur. Therefore SYNCA should not rise in the range of ±500ns from t1.

Data slip means that data is deleted or the same data is output twice.

(A)

(B)

(2) Through Mode (DECODER Side)

BCLK

ADPCM side SYNC (SYNCA)

ADPCM Input (SIA)

Internal Latch Timing

PCM side SYNC (SYNCP)

PCM side SYNC (SYNCP)

Through-Data Output (SOP)

Through-Data Output (SOP)

t0

t1

12345678

ADPCMDATA1

PCMDATA0

PCMDATA1

PCMDATA2

ADPCMDATA2

ADPCMDATA3

PCMDATA0

PCMDATA1

*t1 is the falling edge of the 8th BCLK counted from t0.

(A) When SYNCA rises after t1, ADPCMDATA1 is output to PCMDATA1.

(B) When SYNCA rises before t1, ADPCMDATA1 is output to PCMDATA1.

If SYNCP rises near the t1 and jitter occurs, data slip may occur. Therefore SYNCA should not rise in the range of ±500ns from t1.

Data slip means that data is deleted or the same data is output twice.

(A)

(B)