I15104F datasheet(8/22 Pages) NUVOTON

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ISD15100 SERIES

Publication Release Date: May 6, 2011

- 8 -

Revision 1.3

PIN DESCRIPTION

Number

Pin Name

I/O

Function

This pin should be left unconnected.

2S_SDI/

GPIO7

Serial Data Input of the I

2S interface (If I2S is not used, this pin should

be grounded).

Or, can be configured as a GPIO pin.

2S_SCK/

GPIO6

I/O

Clock input in slave mode or clock output in master mode. This pin can

be configured as an external clock buffer if I

2S is not used (If I2S is not

used, this pin should be grounded).

Or, can be configured as a GPIO pin.

2S_WS/

GPIO5

I/O

Word Select (WS) input in slave mode or WS output in master mode (If

I2S is not used, this pin should be grounded).

Or, can be configured as a GPIO pin.

2S_SDO/

GPIO4

Serial Data Output of the I

2S Interface (If I2S is not used, this pin

should be left unconnected).

Or, can be configured as a GPIO pin.

VCCD

Digital power supply.

VSSD

Digital Ground.

VSSD

Digital Ground.

VCCD

Digital power supply.

VREG

A 1.8V regulator to supply the internal logic. A 0.1uF capacitor should

be connected to this pin for supply decoupling and stability.

MISO

Master-In-Slave-Out. Serial output from the ISD15100 to the host. This

pin is in tri-state when SSB=1.

SCLK

Serial Clock input to the ISD15100 from the host.

SSB

Slave Select input to the ISD15100 from the host. When SSB is low

device is selected and responds to commands on the SPI interface.

MOSI

Master-Out-Slave-In. Serial input to the ISD15100 from the host.

VCCD_PWM

Digital Power for the PWM Driver.

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