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UP9503P bảng dữ liệu(PDF) 12 Page - uPI Group Inc.

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UP9503P bảng dữ liệu(HTML) 12 Page - uPI Group Inc.

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uP9503P
12
uP9503P-DS-F0000, June 2017
www.upi-semi.com
Functional Description
DAC Reference Voltage
The uP9503P embeds separate precise bandgap reference
voltage generation circuits for VDD and VDDA controllers.
Figure 4 shows the reference voltage generation circuit.
The output voltage of bandgap reference circuit is 1.55V
with respect to FBRTN (FBRTNA for VDDA).
The uP9503P utilizes plural resistors to generate precise
reference voltages ranging from 6.25mV to 1.55V, with
6.25mV step. All the voltages connect to a multiplexer
(MUX). According to SVI2 command, the MUX outputs the
selected VID (VDAC) to the current limit buffer input. The
DAC voltage is generated as the reference voltage to the
DAC pin (DACA pin for VDDA). The DAC voltage for VDDA
is generated by the same method except that it is referred
to FBRTNA pin. Table 6 shows the VID voltage and the
SVI2 code.
VBG
FBRTN
1.55V
FBRTN
RN
R2
R1
+
-
1.55V
6.25mV
MUX
6.25mV~1.55V
Step=6.25mV
VDAC
SVI2
Interface
Current
Limited
Buffer
Figure 4. Reference Voltage Generation Circuit
Dynamic VID Change and Slew Rate
The controller accepts SetVID command via SVI2 bus for
output voltage change during normal operation. This allows
the output voltage to change while the DC/DC converter is
running and supplying current to the load. This is commonly
referred to as VID on-the-fly (VID OTF). A VID OTF event
may occur under either light or heavy load condition. This
voltage change direction can be upward or downward. The
default value of VID upward slew rate is 12mV/us. The value
of VID downward slew rate is 1/3 of VID upward slew rate.
The upward slew rate of VDD and VDDA can be separately
further programmed by the controllers SMBus register
0x26h. The upward slew rate can be set from 8mV/us to
22mV/us with a total of 7 steps and 2mV/LSB resolution.
The default value of upward slew rate is 12mV/us.
Output Voltage Differential Sense
The uP9503P uses differential sense by a high-gain low
offset error amplifier for output voltage differential sense as
shown in Figure 5. The GPU voltage is sensed by the FB
and FBRTN pins (FBA and FBRTNA for VDDA). FB pin is
connected to the positive remote sense pin VDD_SENSE
of the GPU via the resistor R
FB. FBRTN pin is connected to
the negative remote sense pin VSS_SENSE of GPU
directly. (VDDA_SENSE and VSSA_SENSE for VDDA).
The error amplifier compares the V
FB with VEAP (=VDAC - IMON
x R
DRP) to regulate the output voltage.
Gm
RCOMP_INT
COMP
FB
RFB
VDD_SENSE
Positive voltage remote
sense pin of GPU
CSP
CSN
EAP
DAC
RDRP
FBRTN
CDAC
VSS_SENSE
Negative voltage remote
sense pin of GPU
CCOMP
RCSN
CCSN
Reference
Voltage
RCOMP
IMON
Figure 5. Output Voltage Differential Sense
Total Load Current Sense
The uP9503P uses a low input offset current sense amplifier
(CSA) to sense the total load current flowing through
inductors for droop function by CSP and CSN (CSPA and
CSNA for VDDA) as shown in Figure 6.
RPH2
RPH3
1ohm
PH1
PH2
PH3
1ohm
1ohm
VDD_1
VDD_2
VDD_3
CCSN
RCSN
CSP
CSN
RPH1
IMON
Figure 6.Total Load Current Sense
The voltage across C
CSN is proportional to the total load
current, and the output current of CSA (I
MON) is also
proportional to the total load current of the voltage regulator.
The sensed current I
MON represents the total output current
of the regulator, and it is directly used for droop function,
total output over current protection, and output current
reporting. I
MON is calculated as follows.
CSN
DC
OUT
MON
R
P
R
I
I
×
=
In this inductor current sensing topology, R
PH and CCSN must
be selected according to the equation below:
P
C
R
R
L
k
CSN
PH
DC
×
=
×
where R
DC is the DCR of the output inductor L, P is the
operation phase number. Theoretically, k should be equal
to 1 to sense the instantaneous total load current. But in
real application, k is usually between 1.2 to 1.8 for better
load transient response. Note that the resistance value of
R
CSN must be less than 2k
Ω
to ensure the current sensing
circuit in normal operation.



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