SCD1284 datasheet(154/176 Pages) INTEL

154 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

154

Datasheet

slow masters that require an ACK* pulse longer than the maximum specified in the IEEE STD

1284 specification. The table below shows some examples of the necessary binary value for

various system clock frequencies to set the 500-ns pulse width.

7.9

Pin Control Registers

The parallel port has five outputs and four inputs. The pin assignments are the same as those

defined in the IEEE STD 1284 specification. The definition of the pins depends on the current

negotiated mode; these are detailed in the following descriptions.

7.9.1

Signal Status Register

The bits in this register show the results of changes specified in the ODR and ZDR. Normally, the

host reads this register in response to a signal change interrupt generated by the CD1284. This

value to the register clears it.

7.9.2

Zeros Detect Register

Setting the bits in this register enables the CD1284 to generate an interrupt – if the SigCh bit

(PCIER[4]) is set – when the selected signal changes from high-to-low (falling edge). Bits 7:4 are

reserved and must be written as ‘0’; they return ‘0’ when read. The settings in this register have no

effect (that is, the SigCh interrupt is not generated) unless the device is in Manual mode.

Clock

(MHz)

SPR Value

Resultant Pulse Width

(ns)

500

520

Access: Read/Write

8-Bit Hex Address: 2F

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A1284

nInit

HstBsy

HstClk

Access: Read/Write

8-Bit Hex Address: 2C

Default Value: 00

A1284

nInit

HstBsy

HstClk

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