SCD1284 datasheet(136/176 Pages) INTEL

136 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

136

Datasheet

7.6.10

Transmit Clock Option Register

The TCOR selects the clock source which drives the TBPR. The value in ClkSel[2:0] selects one of

five possible clocks generated from the master clock (CLK).

7.7

Channel Registers — Parallel Pipeline

7.7.1

Data Error Register

The bits in this read-only register indicate read/write errors involving the DMABUF register and

the Data Pipeline registers. The DataErr bit (PFSR[0]) is the logical OR of these eight Error Status

bits.

Reading this register has no effect on the error status. A write to this register clears all the bits,

which cannot be written by the user. Host software should clear this register (write x’00) after

completing an error service-acknowledge procedure. This bit is provided primarily as an aid to

driver software development. Data errors should never occur under normal circumstances.

This register is cleared during device reset.

Access: Read/Write

8-Bit Hex Address: 76

Default Value: 01

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ClkSel2

ClkSel1

ClkSel0

ClkSel2

ClkSel1

ClkSel0

Clock Selected

Clk0 (CLK

÷ 8)

Clk1 (CLK

÷ 32)

Clk2 (CLK

÷ 128)

Clk3 (CLK

÷ 512)

Clk4 (CLK

÷ 2048)

Not used.

Access: Read only

8-Bit Hex Address: 33

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMAwrerr

DMArderr

Bufwrerr

Bufrderr

HR1wrerr

HR1rderr

HR2wrerr

HR2rderr

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