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AD9144BCPZ bảng dữ liệu(PDF) 83 Page - Analog Devices |
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AD9144BCPZ bảng dữ liệu(HTML) 83 Page - Analog Devices |
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83 / 125 page  Data Sheet AD9144 Rev. B | Page 83 of 125 START-UP SEQUENCE Table 87 through Table 96 show the register writes needed to set up the AD9144 with fDAC = 1474.56 MHz, 2× interpolation, and the DAC PLL enabled with a 368.64 MHz reference clock. The JESD204B interface is configured in Mode 4, dual-link mode, Subclass 1, and scrambling is enabled with all eight SERDES lanes running at 7.3728 Gbps, inputting twos complement formatted data. No remapping of lanes with the crossbar is done in this example. The sequence of steps to properly start up the AD9144 are as follows: 1. Set up the SPI interface, power up necessary circuit blocks, make required writes to the configuration register, and set up the DAC clocks (see the Step 1: Start Up the DAC section). 2. Set the digital features of the AD9144 (see the Step 2: Digital Datapath section). 3. Set up the JESD204B links (see the Step 3: Transport Layer section). 4. Set up the physical layer of the SERDES interface (see the Step 4: Physical Layer section). 5. Set up the data link layer of the SERDES interface. This procedure is for quick startup or debug only and does not guarantee deterministic latency (see the Step 5: Data Link Layer section). 6. Check for errors on Link 0 and Link 1 (see the Step 6: Error Monitoring section). These steps are outlined in detail in the following sections in tables that list the required register write and read commands. STEP 1: START UP THE DAC Power-Up and DAC Initialization Table 87. Power-Up and DAC Initialization Command Address Value Description W 0x000 0xBD Soft reset W 0x000 0x3C Deassert reset, set 4-wire SPI W 0x011 0x00 Enable reference, DAC channels, and master DAC W 0x080 0x00 Power up all clocks W 0x081 0x00 Power up SYSREF receiver, disable hysteresis Required Device Configurations Table 88. Required Device Configuration Command Address Value Description W 0x12D 0x8B Digital datapath configuration W 0x146 0x01 Digital datapath configuration W 0x2A4 0xFF Clock configuration W 0x232 0xFF SERDES interface configuration W 0x333 0x01 SERDES interface configuration Step 1A: Configure the DAC PLL Table 89. Configure DAC PLL Command Address Value Description W 0x087 0x62 Optimal DAC PLL loop filter settings W 0x088 0xC9 Optimal DAC PLL loop filter settings W 0x089 0x0E Optimal DAC PLL loop filter settings W 0x08A 0x12 Optimal DAC PLL charge pump settings W 0x08D 0x7B Optimal DAC LDO settings for DAC PLL W 0x1B0 0x00 Power DAC PLL blocks when power machine is disabled W 0x1B9 0x24 Optimal DAC PLL charge pump settings W 0x1BC 0x0D Optimal DAC PLL VCO control settings W 0x1BE 0x02 Optimal DAC PLL VCO power control settings W 0x1BF 0x8E Optimal DAC PLL VCO calibration settings W 0x1C0 0x2A Optimal DAC PLL lock counter length setting W 0x1C1 0x2A Optimal DAC PLL charge pump setting W 0x1C4 0x7E Optimal DAC PLL varactor settings W 0x08B 0x02 Set the VCO LO divider to 8 so that 6 GHz ≤ fVCO = fDACCLK × 2(LODivMode + 1) ≤ 12 GHz W 0x08C 0x03 Set the reference clock divider to 8 so that the reference clock into the PLL is less than 80 MHz W 0x085 0x10 Set the B counter to 16 to divide the DAC clock down to 2× the reference clock W 0x1B5 0x09 PLL lookup value from Table 25 for fVCO ≥ 7.25GHz W 0x1BB 0x13 PLL lookup value from Table 25 for fVCO ≥ 7.25GHz W 0x1C5 0x06 PLL lookup value from Table 25 for fVCO ≥ 7.25GHz W 0x083 0x10 Enable DAC PLL R 0x084 0x01 Verify that Bit 1 reads back high for PLL locked STEP 2: DIGITAL DATAPATH Table 90. Digital Datapath Command Address Value Description W 0x112 0x01 Set the interpolation to 2× W 0x110 0x00 Set twos complement data format |
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