DAC5686IPZP datasheet(22/46 Pages) TI

tên linh kiện	DAC5686IPZP

Giải thích chi tiết về linh kiện	16-BIT, 500-MSPS, 2X16X INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER

PDF	46 Pages

Scroll/Zoom	100%

nhà sản xuất	TI [Texas Instruments]

Trang chủ	http://www.ti.com

Logo

22 / 46 page

www.ti.com

R/W

tSCLKL

SDENB

SCLK

SDIO

N1 N0

−

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDENB

SCLK

SDIO

Instruction Cycle

Data Transfer Cycle(s)

ts(SDENB)

tSCLK

th(SDIO)

ts(SDIO)

tSCLKH

R/W

SDENB

SCLK

SDIO

N1 N0

−

A3 A2 A1 A0

D6 D5 D4 D3 D2

D0 0

Instruction Cycle

Data Transfer Cycle(s)

SDO

D7 D6 D5 D4 D3 D2 D1 D0 0

3-Pin Configuration

Output

4-Pin Configuration

Output

SDENB

SCLK

SDIO

Data n

Data n−1

SDO

td(Data)

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

Figure 24. Serial-Interface Write Timing Diagram

Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface

clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial

data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the

data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from

the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin

configuration.

Figure 25. Serial-Interface Read Timing Diagram

DAC5686IPZP bảng dữ liệu(PDF) 22 Page - Texas Instruments

DAC5686IPZP bảng dữ liệu(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL