DAC5686IPZP datasheet(10/46 Pages) TI

10 / 46 page

www.ti.com

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)

over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8

V, IOUT

FS = 20 mA (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IL = 100 µA

0.2

Low-level output voltage,

VOL

PLLLOCK, SDO, SDIO (I/O)

IL = 8 mA

0.22

× IOVDD

PLL

Input data rate supported

160

MSPS

At 600-kHz offset, measured at

DAC output, 25-MHz 0-dBFS tone,

128

fDATA = 125 MSPS, 4× interpolation

Phase noise

dBc/Hz

At 6-MHz offset, measured at DAC

output, 25-MHz 0-dBFS tone, fDATA

151

= 125 MSPS, 4

× interpolation

VCO minimum frequency

PLL_rng = 00 (nominal)

120

MHz

VCO maximum frequency

PLL_rng = 00 (nominal)

500

MHz

NCO

NCO clock (DAC update rate)

320

MHz

Serial Port Timing

Setup time, SDENB to rising edge

tsu(SDENB)

of SCLK

Setup time, SDIO valid to rising

tsu(SDIO)

edge of SCLK

Hold time, SDIO valid to rising

th(SDIO)

edge of SCLK

tSCLK

Period of SCLK

100

tSCLKH

High time of SCLK

tSCLKL

Low time of SCLK

Data output delay after falling

td(Data)

edge of SCLK

Parallel Data Input Timing (PLL Mode, CLK1 Input)

Setup time, data valid to rising

tsu(DATA)

0.3

–0.4

edge of CLK1

Hold time, data valid after rising

th(DATA)

1.2

0.6

edge of CLK1

Parallel Data Input Timing (Dual Clock Mode, CLK1 and CLK2 Input)

Setup time, data valid to rising

tsu(DATA)

–0.4

edge of CLK1

Hold time, data valid after rising

th(DATA)

0.6

edge of CLK1

Timing Parallel Data Input (External Clock Mode, CLK2 Input)

High-impedance load on PLLLOCK.

Setup time, DATA valid to rising

tsu(DATA)

Note that tsu increases with a

4.6

edge of PLLLOCK

lower-impedance load.

High-impedance load on PLLLOCK.

Hold time, DATA valid after rising

Note that th decreases (becomes

th(DATA)

–0.8

–2.4

edge of PLLLOCK

more negative) with a

lower-impedance load.

High-impedance load on PLLLOCK.

Delay from CLK2 rising edge to

Note that PLLLOCK delay in-

td(PLLLock)

2.5

4.2

6.5

PLLLOCK rising edge

creases with a lower-impedance

load.

DAC5686IPZP bảng dữ liệu(PDF) 10 Page - Texas Instruments

DAC5686IPZP bảng dữ liệu(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL