DAC5686IPZP datasheet(21/46 Pages) TI

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Serial-Port Timing Diagrams

DAC5686

SLWS147B – APRIL 2003 – REVISED AUGUST 2004

DETAILED DESCRIPTION (continued)

Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from

which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a

detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred.

Table 1. Instruction Byte of the Serial Interface

MSB

LSB

Bit

Description

R/W

–

R/W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation

from the DAC5686 and a low indicates a write operation to the DAC5686.

N[1:0]: Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB-first.

Table 2. Number of Transferred Bytes Within One

Communication Frame

DESCRIPTION

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

A4: Unused

A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte

transfers, this address is the starting address and the address decrements. Note that the address is written to the

DAC5686 MSB-first.

Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface

clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial

data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK.

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