November 22, 2004

25

Philips Semiconductors

Preliminary specification

Universal LCD driver

for low multiplex rates

PCF8562

Table 12 Blink option 1

Table 13 Blink option 2

Note

1.

Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected.

7.9

Display controller

The display controller executes the commands identified by the command decoder. It contains the device’s status

registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display

RAM in the correct filling order.

7.10

Multiple chip operation

For large display configurations please refer to the PCF8576D device.

Please refer to PCF8576D if you need to drive more segments (>128 elements).

BLINK FREQUENCY

BITS

BF1

BF0

Off

0

0

2 Hz

0

1

1 Hz

1

0

0.5 Hz

1

1

BLINK MODE

BIT A

Normal blinking

0

Alternate RAM bank blinking

1