công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

AD9577BCPZ-R7 bảng dữ liệu(PDF) 12 Page - Analog Devices

tên linh kiện AD9577BCPZ-R7
Giải thích chi tiết về linh kiện  Clock Generator with Dual PLLs, Spread Spectrum, and Margining
PDF  44 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD9577BCPZ-R7 bảng dữ liệu(HTML) 12 Page - Analog Devices

Back Button AD9577BCPZ-R7 Datasheet HTML 8Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 9Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 10Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 11Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 12Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 13Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 14Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 15Page - Analog Devices AD9577BCPZ-R7 Datasheet HTML 16Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 44 page
background image
AD9577
Data Sheet
Rev. A | Page 12 of 44
TIMING CHARACTERISTICS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL (see Figure 2)
Termination = 200 Ω to 0 V, ac-coupled to 50 Ω
oscilloscope; CLOAD = 5 pF
Output Rise Time, tRP
170
225
300
ps
20% to 80%, measured differentially
Output Fall Time, tFP
170
230
310
ps
80% to 20%, measured differentially
Skew
20
ps
Between the outputs of the same PLL at the
same frequency. SyncCh01/SyncCh23 set to 1
LVDS (see Figure 3)
Termination = 100 Ω differential; CLOAD = 5 pF
Output Rise Time, tRL
180
250
340
ps
20% to 80%, measured differentially
Output Fall Time, tFL
180
260
330
ps
80% to 20%, measured differentially
Skew
20
ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
CMOS (see Figure 4)
Output Rise Time, tRC
250
680
950
ps
Termination is high impedance active probe,
total CLOAD = 5 pF, RLOAD = 20 kΩ, 20% to 80%
Output Fall Time, tFC
350
700
1000
ps
Termination is high impedance active probe,
total CLOAD = 5 pF, RLOAD = 20 kΩ, 80% to 20%
Skew
20
ps
Between the outputs of the same PLL at the
same frequency; SyncCh01/SyncCh23 set to 1
Timing Diagrams
DIFFERENTIAL
LVPECL
80%
50%
20%
tRP
VOD
tFP
Figure 2. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
50%
20%
tRL
VOD
tFL
Figure 3. LVDS Timing, Differential
SINGLE-ENDED
CMOS
80%
20%
tRC
tFC
Figure 4. CMOS Timing, Single-Ended, 5 pF Load



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com