LPC802 datasheet(15/83 Pages) NXP

15 / 83 page

LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

15 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

9. Functional description

9.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 15 MHz using a

two-stage pipeline. The core revision is r0p1.

Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two

watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast

GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

9.2 On-chip flash program memory

The LPC802 contain up to 16 KB of on-chip EEPROM based flash program memory.

9.3 On-chip SRAM

The LPC802 contain a total of 2 KB on-chip static RAM data memory.

9.4 On-chip ROM

The on-chip ROM contains the bootloader:

• Boot loader.

• Supports Flash In-Application Programming (IAP).

• Supports In-System Programming (ISP) through USART.

• On-chip ROM APIs for integer divide.

• Free Running Oscillator (FRO) API.

9.5 Memory map

The LPC802 incorporates several distinct memory regions. Figure 9 shows the overall

map of the entire address space from the user program viewpoint following reset. The

interrupt vector area supports address remapping.

The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,

the system tick timer (SysTick), and the reduced power modes.

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