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LPC81xM bảng dữ liệu(PDF) 57 Page - NXP Semiconductors

tên linh kiện LPC81xM
Giải thích chi tiết về linh kiện  32-bit ARM짰 Cortex짰-M0 microcontroller
PDF  78 Pages
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LPC81xM bảng dữ liệu(HTML) 57 Page - NXP Semiconductors

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LPC81XM
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 4.6 — 4 April 2018
57 of 78
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
[1]
CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = 40 C to
+105
C. Typical data are for T
amb = 27 C.
[2]
Input hysteresis is relative to the reference input channel and is software programmable to three levels.
[1]
Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process
models).
[2]
Settling time applies to switching between comparator channels.
tPD
propagation delay
HIGH to LOW; VDD = 3.0 V;
VIC = 0.1 V; 50 mV overdrive input
[1]
-
109
121
ns
VIC = 0.1 V; rail-to-rail input
[1]
-
155
164
ns
VIC = 1.5 V; 50 mV overdrive input
[1]
-95
105
ns
VIC = 1.5 V; rail-to-rail input
[1]
-
101
108
ns
VIC = 2.9 V; 50 mV overdrive input
[1]
-
122
129
ns
VIC = 2.9 V; rail-to-rail input
[1]
-74
82
ns
tPD
propagation delay
LOW to HIGH; VDD = 3.0 V;
VIC = 0.1 V; 50 mV overdrive input
[1]
-
246
260
ns
VIC = 0.1 V; rail-to-rail input
[1]
-57
59
ns
VIC = 1.5 V; 50 mV overdrive input
[1]
-
218
ns
VIC = 1.5 V; rail-to-rail input
[1]
-
146
155
ns
VIC = 2.9 V; 50 mV overdrive input
[1]
-
184
206
ns
VIC = 2.9 V; rail-to-rail input
[1]
-
250
286
ns
Vhys
hysteresis voltage
positive hysteresis; VDD = 3.0 V;
VIC = 1.5 V
[2]
-
6, 11, 21
-
mV
Vhys
hysteresis voltage
negative hysteresis; VDD = 3.0 V;
VIC = 1.5 V
[2][2] -
4, 9, 19
-
mV
Rlad
ladder resistance
-
-
1.034
-
M
Table 22.
Comparator characteristics …continued
VDD = 3.0 V and Tamb = 27 C unless noted otherwise.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 23.
Comparator voltage ladder dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ts(pu)
power-up settling
time
to 99% of voltage
ladder output
value
[1] --
30
s
ts(sw)
switching settling
time
to 99% of voltage
ladder output
value
[1]
[2]
--
15
s



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