ADDI7100BCPZ datasheet(13/20 Pages) AD

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Data Sheet

ADDI7100

Rev. E | Page 13 of 20

ANALOG-TO-DIGITAL CONVERTER (ADC)

The ADDI7100 uses a high performance ADC architecture

optimized for high speed and low power. Differential non-

linearity (DNL) performance is typically better than 0.5 LSB.

The ADC uses a 2 V full-scale input range.

VARIABLE GAIN AMPLIFIER (VGA)

The VGA stage provides a gain range of 6 dB to 42 dB, pro-

grammable with 10-bit resolution through the serial digital

interface. The minimum gain of 6 dB is needed to match a 1 V

input signal with the ADC full-scale range of 2 V. A plot of the

VGA gain curve is shown in Figure 13.

VGA Gain (dB) = (VGA Code × 0.0358 dB) + 5.4 dB

where Code is in the range of 0 to 1023.

VGA GAIN REGISTER MODE

383

127

255

511

639

767

895

1023

Figure 13. VGA Gain Curve

DIGITAL DATA OUTPUTS

By default, the digital output data is latched by the rising edge of

the DATACLK input. Output data timing is shown in Figure 3.

It is also possible to make the output data latch transparent,

immediately validating the data outputs from the ADC. Setting

the DOUTLATCH register (Address 0x01[5]) to 1 configures

the latch as transparent. The data outputs can also be disabled

by setting the DOUT_OFF register (Address 0x01[4]) to 1.

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