DLPC6421 datasheet(34/48 Pages) TI1

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DLPC6421

DLPS117 – JULY 2018

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9.3 Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the DLPC6421 device minimum supply voltage spec.

Thus for practical reasons, TI recommends that the external power monitor generating POSENSE target its

threshold to 90% of the minimum supply voltage specs and ensure that POSENSE remain low a sufficient

amount of time for all supply voltages to reach minimum device requirements and stabilize. Note that the trip

voltage for detecting the loss of power, as well as the reaction time to respond to a low voltage condition is not

critical for POSENSE as PWRGOOD is used for this purpose. As such, PWRGOOD has critical requirements in

these areas.

9.4 System Environment and Defaults

9.4.1 DLPC6421 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC6421 device performs a power-up initialization routine that defaults the

device to it’s normal power mode, in which ARM9-related clocks are enabled at their full rate and associated

resets are released. Most other clocks default to disabled state with associated resets asserted until released by

the processor. In addition, the default for system power gating enables all power. These same defaults are also

applied as part of all system reset events (Watch Dog timer timeout, reset, etc) that occur without removing or

cycling power, with the possible exception of power for the LVDS I/O and internal DRAM.

Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it

enables the rest of the DLPC6421 clocks, and initializes the internal DRAM.

9.4.2 1.1-V System Power

The DLPC6421 device can support a low cost power delivery system with a single 1.1-V power source derived

from a switching regulator. To enable this approach, appropriate filtering must be provided for the 1.1-V power

pins of the PLLs.

9.4.3 1.8-V System Power

TI recommends that the DLPC6421 device power delivery system provide two independent 1.8-V power sources.

One of the 1.8-V power sources should be used to supply 1.8-V power to the DLPC6421 device LVDS I/O and

internal DRAM. Power for these functions should always be fed from a common source which is recommended

to be linear regulator. The second 1.8-V power source should be used (along with appropriate filtering as

discussed in the PCB layout guidelines for internal DLPC6421 PLL power section of this document) to supply all

of the DLPC6421 device internal PLLs. In order to keep this power as clean as possible, TI highly recommends a

dedicated linear regulator for the 1.8-V power to the PLLs.

9.4.4 3.3-V System Power

The DLPC6421 device can support a low cost power delivery system with a single 3.3-V power sources derived

from a switching regulator. This 3.3-V power will supply all LVTTL I/O and the Crystal Oscillator cell. 3.3-V power

should remain active in all power modes for which 1.1-V core power is applied.

9.4.5 Power Good (PWRGOOD) Support

The PWRGOOD signal is defined as an early warning signal that alerts the DLPC6421 device a specified amount

of time before the DC supply voltages drop below specifications. This allows the DLPC6421 device to park the

DMD and to place the system into reset, ensuring the integrity of future operation. For practical reasons, TI

recommends that the monitor sensing PWRGOOD be on the input side of supply regulators.

9.4.6 I2C BUSY (I2C_BUSY)

The I2C_BUSY signal indicates when the system is ready to accept incoming commands from the front end,

polling is recommended to ensure all I2C transactions are accepted and processed.

9.4.7 5V Tolerant Support

With the exception of USB_DAT, the DLPC6421 device does not support any other 5V tolerant I/O.

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