DLPC6421 datasheet(33/48 Pages) TI1

33 / 48 page

1.1 V

(ASIC PLL)

3.3 V

(ASIC I/O)

1.8 V

(LVDS I/O & Internal

DRAM)

1.8 V

(ASIC PLL)

1.1 V

(ASIC Core)

POSENSE

DLPC6421

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DLPS117 – JULY 2018

Product Folder Links: DLPC6421

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9 Power Supply Recommendations

9.1 System Power Regulations

TI strongly recommends that the VDD18_PLLD, VDD18_PLLM1, and VDD18_PLLM2 power feeding internal

PLLs be derived from an isolated linear regulator in order to minimize the AC noise component. It is acceptable

for VDD11_PLLD, VDD11_PLLM1, VDD11_PLLM2, and VDD11_PLLS to be derived from the same regulator as

the core VDD11, but they should be filtered.

9.2 System Power-Up Sequence

Although the DLPC6421 controller requires an array of power supply voltages (1.1 V, 1.8 V, 3.3 V), there are no

restrictions regarding the relative order of power supply sequencing. This is true for both power-up and power-

down scenarios. Similarly, there is no minimum time between powering-up or powering-down the different

supplies feeding the DLPC6421 controller. However, note that it is not uncommon for there to be power

sequencing requirements for the devices that share the supplies with the DLPC6421 controller.

•

1.1-V core power should be applied whenever any I/O power is applied. This ensures the state of the

associated I/O that are powered are controlled to a known state. Thus, TI recommends applying core power

first. Other supplies should be applied only after the 1.1-V core has ramped up.

•

All DLPC6421 device power should be applied before POSENSE is asserted to ensure proper power-up

initialization is performed.

It is assumed that all DLPC6421 device power-up sequencing is handled by external hardware. It is also

assumed that an external power monitor will hold the DLPC6421 device in system reset during power-up (i.e.

POSENSE = 0). During this time all DLPC6421 device I/O will be tri-stated. The master PLL (PLLM1) is released

from reset upon the low to high transition of POSENSE but the DLPC6421 device keeps the rest of the device in

reset for an additional 60 ms to allow the PLL to lock and stabilize its outputs. After this 60 ms delay the ARM-9

related internal resets will be de-asserted causing the microprocessor to begin its boot-up routine. PROJ_ON is

used to trigger the final step of the boot up routine, polling of GPIO_56 (I2C_BUSY/SYSTEM_BUSY) can be

used by the front end to determine when to assert PROJ_ON.

Figure 13. System Power-Up Sequence

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