PC7410 datasheet(40/54 Pages) ATMEL

40 / 54 page

PC7410

2141D–HIREL–02/04

The PC7410 generates the clock for the external L2 synchronous data SRAMs by divid-

ing the core clock frequency of the PC7410. The divided-down clock is then phase-

adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the

PC74107410 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out

half the distance to the SRAMs and then returned as an input to the DLL on pin

L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be

aligned to the clocking of the internal latches in the L2 bus interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of

the L2CR register. Generally, the divisor must be chosen according to the frequency

supported by the external RAMs, the frequency of the PC7410 core, and the phase

adjustment range that the L2 DLL supports. Table 18 shows various example L2 clock

frequencies that can be obtained for a given set of core frequencies. The minimum L2

frequency target is 133 MHz. Sample core-to-L2 frequencies for the PC7410 is shown in

Table 18. In this example, shaded cells represent settings that, for a given core fre-

quency, result in L2 frequencies that do not comply with the minimum and maximum L2

frequencies listed in Table 14.

Note:

The core and L2 frequencies are for reference only. Some examples may represent core

or L2 frequencies which are not useful, not supported or not tested for by the PC7410;

see “L2 Clock AC Specifications” on page 23 for valid L2CLK frequencies. The

L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz.

System Design

Information

PLL and DLL Power

Supply Filtering

The AV

DD and L2AVDD power signals are provided on the PC7410 to supply power to

the PLL and DLL, respectively.

On systems that use the PC7410 CBGA device, the L2AV

DD filter should implement the

circuit shown in Figure 28. The AV

DD filter on the PC7410 CBGA device should imple-

ment the circuit shown in Figure 29.

On systems that use the PC7410 HITCE device, the AV

DD and L2AVDD input signals

should both implement the circuit shown in Figure 28.

The circuit shown below should be placed as close as possible to the AV

DD pin to mini-

mize noise coupled from nearby circuits. A separate circuit should be placed as close as

possible to the L2AV

DD pin. It is often possible to route directly from the capacitors to the

DD pin, which is on the periphery of the 360 CBGA footprint, without the inductance of

vias. The L2AV

DD pin may be more difficult to route, but is proportionately less critical.

Table 18. Sample Core-to-L2 Frequencies

Core Frequency in MHz

÷1÷1.5÷2÷2.5

÷3

÷3.5÷4

350

233

175

140

–

366

244

183

147

–

400

266

200

160

133

–

433

–

288

216

173

144

–

450

–

300

225

180

150

–

466

–

311

233

186

155

133

–

500

–

333

250

200

166

143

–

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