PC7410 datasheet(24/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

L2 input and output signals are latched or enabled respectively by the internal L2CLK

(which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK

frequency). In other words, the AC timings of Table 13 are entirely independent of

L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board

trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA

and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since

in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK,

the signals of Table 13 are referenced to this signal rather than the not-externally-visible

internal L2CLK. During manufacturing test, these times are actually measured relative to

SYSCLK.

Notes:

1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency set-

tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum

or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and

L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to

compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap

back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and

the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects

L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and

does not have to be considered in the L2 timing analysis.

Table 12. L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 4)

Symbol

Parameter

400 MHz

450 MHz

500 MHz

Unit

Min

Max

Min

Max

Min

Max

L2CLK

(1)(4)

L2CLK frequency

133

400

133

400

133

400

MHz

tL2CLK

L2CLK cycle time

2.5

7.5

2.5

7.5

2.5

7.5

tCHCL/tL2CLK

(2)

L2CLK duty cycle

Internal DLL-relock time(3)

640

L2CLK

DLL capture window(5)

010010010

tL2CSKW

L2CLKOUT output-to-output

skew(6)

-50-50

-50

L2CLKOUT output jitter(6)

±150

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