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HMC974LC3CTR-R5 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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HMC974LC3CTR-R5 bảng dữ liệu(HTML) 9 Page - Analog Devices |
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9 / 12 page ![]() Data Sheet HMC974LC3C Rev. E | Page 9 of 12 THEORY OF OPERATION The HMC974LC3C is a window comparator where the range of the window is defined with RT as the top of the voltage window range and RB as the bottom of the voltage window range. The comparator has two modes of operation: track mode and latch mode. While in track mode, the comparator determines three things: 1. If the signal is below the window voltage value, RT, and above the window voltage value, RB, represented by the WOUTB output. 2. If the signal is above the window voltage value RT, which is represented by the ORB output. 3. If the signal is below the window voltage value RB, which is represented by the URB output. A typical 5 Gbps output eye is shown in Figure 12 with specific details outlined in Table 4. TIME (33.3ps/DIV) EDGE SAMPLES Figure 12. Eye Diagram at 5 Gbps Table 4. Eye Diagram Details Parameter Value Bit Rate 5 Gbps Pattern Length 215 − 1 Deterministic Jitter (Peak-to-Peak) 2.15 ps Vertical Scale 80 mV/div Time Scale 33.3 ps/div POWER SEQUENCING Use the following supplies sequentially to power up the device: 1. VEE 2. VCCI and VCCO (if VCCO = VCCI) 3. VCCO (if different than ground) The power-down sequence is the reverse of the previous sequence: 1. VCCO (if different than ground) 2. VCCI and VCCO (if VCCO = VCCI) 3. VEE Apply power to the HMC974LC3C before applying the input signals (WIN and WIT) and remove the input signals (WIN and WIT) prior to powering it down. |
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