KMB-001LEVALZ datasheet(25/34 Pages) RENESAS

25 / 34 page

ISLA214P12

FN7982 Rev 2.00

Page 25 of 34

June 27, 2012

Serial Peripheral Interface

A serial peripheral interface (SPI) bus is used to facilitate

configuration of the device and to optimize performance. The

SPI bus consists of chip select (CSB), serial clock (SCLK) serial

data output (SDO), and serial data input/output (SDIO). The

maximum SCLK rate is equal to the A/D sample rate (fSAMPLE)

divided by 16 for both write operations and read operations. At

fSAMPLE = 125MHz, maximum SCLK is 7.8125MHz for writing

and read operations. There is no minimum SCLK rate.

The following sections describe various registers that are used to

configure the SPI or adjust performance or functional parameters.

Many registers in the available address space (0x00 to 0xFF) are

not defined in this document. Additionally, within a defined

reserved. Undefined registers and undefined values within defined

registers are reserved and should not be selected. Setting any

reserved register or value may produce indeterminate results.

SPI Physical Interface

The serial clock pin (SCLK) provides synchronization for the data

transfer. By default, all data is presented on the serial data

input/output (SDIO) pin in three-wire mode. The state of the SDIO

pin is set automatically in the communication protocol

(described in the following). A dedicated serial data output pin

(SDO) can be activated by setting 0x00[7] high to allow operation

in four-wire mode.

The SPI port operates in a half duplex master/slave

configuration, with the ISLA214P12 functioning as a slave.

Multiple slave devices can interface to a single master in

three-wire mode only, since the SDO output of an unaddressed

device is asserted in four wire mode.

The chip-select bar (CSB) pin determines when a slave device is

being addressed. Multiple slave devices can be written to

concurrently, but only one slave device can be read from at a

given time (again, only in three-wire mode). If multiple slave

devices are selected for reading at the same time, the results will

be indeterminate.

The communication protocol begins with an instruction/address

phase. The first rising SCLK edge following a high-to-low

transition on CSB determines the beginning of the two-byte

instruction/address command; SCLK must be static low before

the CSB transition. Data can be presented in MSB-first order or

LSB-first order. The default is MSB-first, but this can be changed

by setting 0x00[6] high. Figures 36 and 37 show the appropriate

bit ordering for the MSB-first and LSB-first modes, respectively. In

MSB-first mode, the address is incremented for multi-byte

transfers, while in LSB-first mode it’s decremented.

In the default mode, the MSB is R/W, which determines if the

data is to be read (active high) or written. The next two bits, W1

and W0, determine the number of data bytes to be read or

written (see Table 4). The lower 13 bits contain the first address

for the data transfer. This relationship is illustrated in Figure 38,

and timing values are given in “Switching Specifications” on

page 13.

After the instruction/address bytes have been read, the

appropriate number of data bytes are written to or read from the

A/D (based on the R/W bit status). The data transfer will

continue as long as CSB remains low and SCLK is active. Stalling

of the CSB pin is allowed at any byte boundary

(instruction/address or data) if the number of bytes being

transferred is three or less. For transfers of four bytes or more,

CSB is allowed to stall in the middle of the instruction/address

bytes or before the first data byte. If CSB transitions to a high

state after that point the state machine will reset and terminate

the data transfer.

Figures 40 and 41 on page 24 illustrate the timing relationships

for 2-byte and N-byte transfers, respectively. The operation for a

3-byte transfer can be inferred from these diagrams.

SPI Configuration

ADDRESS 0X00: CHIP_PORT_CONFIG

Bit ordering and SPI reset are controlled by this register. Bit order

can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB

first) to accommodate various micro controllers.

Bit 7 SDO Active

Bit 6 LSB First

Setting this bit high configures the SPI to interpret serial data

as arriving in LSB to MSB order.

Bit 5 Soft Reset

Setting this bit high resets all SPI registers to default values.

Bit 4 Reserved

This bit should always be set high.

Bits 3:0 These bits should always mirror bits 4:7 to avoid

ambiguity in bit ordering.

ADDRESS 0X02: BURST_END

If a series of sequential registers are to be set, burst mode can

improve throughput by eliminating redundant addressing. The

burst is ended by pulling the CSB pin high. Setting the burst_end

address determines the end of the transfer; during a write

operation, the user must be cautious to transmit the correct

number of bytes based on the starting and ending addresses.

Bits 7:0 Burst End Address

This register value determines the ending address of the burst

data.

TABLE 4. BYTE TRANSFER SELECTION

[W1:W0]

BYTES TRANSFERRED

4 or more

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