KMB-001LEVALZ datasheet(5/34 Pages) RENESAS

5 / 34 page

ISLA214P12

FN7982 Rev 2.00

Page 5 of 34

June 27, 2012

Pin Descriptions - 72 Ld QFN, CMOS Mode

PIN NUMBER

CMOS PIN NAME

CMOS PIN FUNCTION

DDR MODE COMMENTS

1, 2, 16, 17, 28, 30, 33,

35, 37, 39, 41, 43, 47,

49, 51, 53, 55, 57, 59, 63

DNC

Do Not Connect

6, 13, 19, 20, 21, 70, 71,

AVDD

1.8V Analog Supply

5, 7, 12, 14

AVSS

Analog Ground

27, 32, 62

OVDD

1.8V Output Supply

26, 45, 61, 65

OVSS

Output Ground

NAPSLP

Tri-Level Power Control (Nap, Sleep modes)

VCM

Common Mode Output

8, 9

VINN

Analog Input Negative

10, 11

VINP

Analog Input Positive

CLKDIV

Tri-Level Clock Divider Control

RESETN

Power On Reset (Active Low)

22, 23

CLKP, CLKN

Clock Input True, Complement

24, 25

CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement

D13

CMOS Bit 13 (MSB) Output

NC in DDR Mode

D12

CMOS Bit 12 Output

DDR Logical Bits 12, 13

D11

CMOS Bit 11 Output

NC in DDR Mode

D10

CMOS Bit 10 Output

DDR Logical Bits 10, 11

CMOS Bit 9 Output

NC in DDR Mode

CMOS Bit 8 Output

DDR Logical Bits 8, 9

CMOS Bit 7 Output

NC in DDR Mode

CMOS Bit 6 Output

DDR Logical Bits 6, 7

RLVDS

LVDS Bias Resistor (connect to OVSS with 1% 10k

)

CLKOUT

CMOS Clock Output

CMOS Bit 5 Output

NC in DDR Mode

CMOS Bit 4 Output

DDR Logical Bits 4, 5

CMOS Bit 3 Output

NC in DDR Mode

CMOS Bit 2 Output

DDR Logical Bits 2, 3

CMOS Bit 1 Output

NC in DDR Mode

CMOS Bit 0 (LSB) Output

DDR Logical Bits 0, 1

CMOS Over Range

DDR Over Range

SDO

SPI Serial Data Output

CSB

SPI Chip Select (active low)

SCLK

SPI Clock

SDIO

SPI Serial Data Input/Output

Exposed Paddle

AVSS

Analog Ground

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