CS5530A datasheet(86/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI.

This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A read-

only (mirror) version of this register exists at F0 Index 84h.

F0 Index F5h

Second Level Power Management Status Register 2 (RC)

Reset Value = 00h

Video Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Video Idle Timer Count Register

(F0 Index A6h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[7].

User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3 Idle

Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[6].

User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF2 Idle

Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[5].

User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF1 Idle

Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[4].

Keyboard/Mouse Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Keyboard/Mouse Idle

Timer Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[3].

Parallel/Serial Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Parallel/Serial Port Idle Timer

Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[2].

Floppy Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Floppy Disk Idle Timer Count

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[1].

Primary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Primary Hard Disk Idle

Timer Count Register (F0 Index 98h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[0].

Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the

duration configured in the Idle Timer Count register for that device, causing an SMI. Reading this register clears the SMI status

bits. A read-only (mirror) version of this register exists at F0 Index 85h. If the value of the register must be read without clearing

the SMI source (and consequently deasserting SMI), F0 Index 85h may be read instead.

F0 Index F6h

Second Level Power Management Status Register 3 (RC)

Reset Value = 00h

Video Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the Video I/O Trap?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[7].

Reserved (Read Only)

Secondary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the

secondary hard disk? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 83h[6].

Table 4-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)

Bit

Description

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