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FDMF3170

Rev. 1.2

3

Pin Configuration

VCC

GL

PGND

GL

1

2

3

4

5

8

9

12

11

10

13

16

28

25

26

27

Top View

PVCC

PGND

5.0mm

PGND

PGND

VIN

VIN

VIN

VIN

VIN

AGND

PGND

PGND

PGND

PGND

PGND

6

7

17

18

19

14

15

20

21

22

23

24

29

30

31

32

33

34

35

36

37

38

39

VOS

40

41

Figure 3.

Pin Configuration

Pin Description

Pin #

Name

Function

1

VOS

VR output voltage sensing pin for pre-OVP protection. Leave it floating if not used.

2

AGND

Analog Ground for the analog portions of the IC and for substrate.

3

VCC

Power Supply input for all analog control functions.

4

PVCC

Power Supply input for LS Gate Driver and Boot Diode.

5, 40

PGND

Reserved for PVCC de-coupling capacitor return.

6, 41

GL

Low-Side Gate Monitor.

7-9, 20-24

PGND

Power ground connection for Power Stage high current path.

10-19

SW

Switching node junction between high-and low-side MOSFETs.

25-30

VIN

Input Voltage to Power Stage.

31

NC

No connect.

32

PHASE

Return Connection for BOOT capacitor.

33

BOOT

Supply for high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies

the charge to turn on the n-channel high side MOSFET. During the freewheeling interval

(LS MOSFET on) the high side capacitor is recharged by an internal diode.

34

PWM

PWM input to gate driver IC.

35

EN

EN=LOW disables most blocks inside IC. EN=HIGH enables all blocks inside IC and

requires 4 µs power up time.

36

TMON / FLT

Temperature and FAULT Reporting Pin. Pin sources a (PTAT) voltage of 0.6 V at 0°C

with an 8 mV/°C slope when no module FAULT is present. In the event of a module

FAULT, this pin pulls HIGH to an internal driver IC rail = 3.0 V typical.

37

N/C

No connect. Some second source options require this pin to be connected.

38

IMON

Current monitor output (output is referenced to REFIN)

– 5 µA/A

39

REFIN

Referenced voltage used for IMON feature. DC input voltage supplied by external source

(not generated on SPS driver IC).