ISL8274M datasheet(25/81 Pages) RENESAS

25 / 81 page

FN8931 Rev.1.00

Page 25 of 81

Jan 4, 2018

ISL8274M

4. Functional Description

The master ISL8274M device in a tracking group is defined as the device that has the highest target output voltage

within the group. This master device will control the ramp rate of all tracking devices and is not configured for

tracking mode. The maximum tracking rise time is 1V/ms. The slave device must be enabled before the master.

Any device that is configured for tracking mode will ignore its TON_DELAY and TON_RISE settings and its

output will take on the turn-on/turn-off characteristics of the reference voltage present at the VTRKP and VTRKN

pins. Tracking mode can be configured by using the TRACK_CONFIG command.

The VOUT_COMMAND needs to be set the same as the target tracking voltage when tracking is enabled. For

example, the VOUT_COMMAND of the Page1 (VOUT2 which enables the tracking) needs to set to 1V if tracking

100% is selected and a ramp of 1V is applied to VTRKP and VTRKN. The VOUT_COMMAND of Page 1

(VOUT2 which enables the tracking) needs to set to 1V if tracking 50% is selected and a ramp of 2V is applied to

VTRKP and VTRKN. In Tracking mode, the minimum voltage that can be tracked is ~200mV.

4.5

Power-Good

The ISL8274M provides a Power-Good (PG) signal that indicates the output voltage is within a specified tolerance

of its target level and no fault condition exists. By default, the PG pin asserts if the output is within 10% of the

target voltage. This limit may be changed using the PMBus command POWER_GOOD_ON.

A PG delay period is defined as the time from when all conditions within the ISL8274M for asserting PG are met to

when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to

control external digital logic. A PG delay can be programmed using the PMBus command

POWER_GOOD_DELAY.

4.6

Switching Frequency and PLL

The device’s switching frequency is set from 296kHz to 1067kHz using the pin-strap method (combined with the

average OCP limit setting) as shown in Table 5, or by using the PMBus command FREQUENCY_SWITCH. The

ISL8274M incorporates an internal Phase-Locked Loop (PLL) to clock the internal circuitry. The PLL can be

driven by an external clock source connected to the SYNC pin. It is recommended that when using an external

clock, the same frequency should be set in the FREQUENCY_SWITCH command. If the external clock is lost, the

module will automatically switch to the internal clock. When using the internal oscillator, the SYNC pin can be

configured as a clock source and as an external sync to other modules. Refer to “SYNC_CONFIG (E9h)” on

page 67 for more information.

Table 5. Switching Frequency and OCP Limit Resistor Setting

SYNC/OCP

OCP Avg

R (kΩ)

Fsw (KHz)

Ch1 (A)

Ch2 (A)

LOW

296

OPEN

889

HIGH

1067

296

12.1

296

13.3

296

14.7

296

16.2

320

17.8

320

19.6

320

21.5

320

23.7

320

26.1

364

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