ISL8274M datasheet(33/81 Pages) RENESAS

33 / 81 page

FN8931 Rev.1.00

Page 33 of 81

Jan 4, 2018

ISL8274M

5. Layout Guide

Layout Guide

To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary

(Figure 32). Refer to the ISL8274MEVAL1Z layout design.

• Establish separate SGND plane and PGND planes, then connect SGND to PGND plane on a middle layer and

underneath PAD6 with a single point connection. For SGND and PGND pin connections, such as small pins H16,

J16, M5 and M17..., use multiple vias for each pin to connect to inner SGND or PGND layers.

• Place enough ceramic capacitors between VIN and PGND, VOUT and PGND and bypass capacitors between VDD,

VDRV and the ground plane, as close to the module as possible to minimize high frequency noise. It is very critical to

place the output ceramic capacitors close to the VOUT pads and in the direction of the load current path in order to

create a low impedance path for the high frequency inductor ripple current.

• Use large copper areas for power paths (VIN, PGND, VOUT) to minimize conduction loss and thermal stress. Also,

use multiple vias to connect the power planes in different layers. It is recommended to enlarge PAD11 and PAD9 to

place more vias on them. The ceramic capacitors CIN can be placed on the bottom layer under these two pads.

• Connect remote sensing traces to the regulation point to achieve a tight output voltage regulation and place the two

traces in parallel. Route a trace from VSEN1/2N and VSEN1/2P to the point of load where the tight output voltage is

desired. Avoid routing any sensitive signal traces, such as the VSENN, VSENP sensing lines near the SW pins.

• PAD14 and 16 (SW1 and SW2) are noisy pads, but they are beneficial for thermal dissipation. If the noise issue is

critical for the applications, it is recommended to use only the top layer for the SW pads. For better thermal

performance, use multiple vias on these pads to connect into the SW inner and bottom layers. However, use caution

when placing a limited area of SW planes in any layer. The SW planes should avoid the sensing signals and should be

surrounded by the PGND layer to avoid noise coupling.

• For pins SWD1 (L3) and SWD2 (P10), it is recommended to connect to the related SW1 and SW2 pads with short

loop traces. The trace width should be more than 20 mils.

Figure 32. Recommended Layout

PGND

VIN

PGND

SGND

VSEN1P

VSEN1N

Kelvin Connections for

Both Ch1 and Ch2

CIN

PGND

COUT1

COUT2

VOUT1

VOUT2

ISL8274M bảng dữ liệu(PDF) 33 Page - Renesas Technology Corp

ISL8274M bảng dữ liệu(HTML) 33 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

bảng dữ liệu tải về

Link URL