ICL7660, ICL7660A

FN3072 Rev.7.00

Page 9 of 11

Oct 5, 2010

10

F:

Since the ESRs of the capacitors are reflected in the output

impedance multiplied by a factor of 5, a high value could

increase in switching frequency or filter capacitance ineffective.

Typical electrolytic capacitors may have ESRs as high as 10



Since the ESRs of the capacitors are reflected in the output

impedance multiplied by a factor of 5, a high value could

increase in switching frequency or filter capacitance ineffective.

Typical electrolytic capacitors may have ESRs as high as 10



Output Ripple

ESR also affects the ripple voltage seen at the output. The total

ripple is determined by 2 voltages, A and B, as shown in Figure

to being discharged through the load (current flowing out of

the total drop is 2

The peak-to-peak ripple voltage is the sum of these voltage

drops:

Again, a low ESR capacitor will reset in a higher performance

output.

Paralleling Devices

Any number of ICL7660 and ICL7660A voltage converters may

be paralleled to reduce output resistance. The reservoir

be approximately:

Cascading Devices

The ICL7660 and ICL7660A may be cascaded as shown to

produced larger negative multiplication of the initial supply

voltage. However, due to the finite efficiency of each device,

the practical limit is 10 devices for light loads. The output

voltage is defined by:

where n is an integer representing the number of devices

cascaded. The resulting output resistance would be

approximately the weighted sum of the individual ICL7660 and

Changing the ICL7660/ICL7660A Oscillator

Frequency

It may be desirable in some applications, due to noise or other

considerations, to increase the oscillator frequency. This is

achieved by overdriving the oscillator from an external clock,

as shown in Figure 17. In order to prevent possible device

latchup, a 1k

 resistor must be used in series with the clock

output. In a situation where the designer has generated the

external clock frequency using TTL logic, the addition of a

10k

 pullup resistor to V+ supply is required. Note that the

pump frequency with external clocking, as with internal

occur on the positive-going edge of the clock.

It is also possible to increase the conversion efficiency of the

ICL7660 and ICL7660A at low load levels by lowering the

oscillator frequency. This reduces the switching losses, and is

shown in Figure 18. However, lowering the oscillator frequency

will cause an undesirable increase in the impedance of the

frequency has been reduced. For example, the addition of a

100pF capacitor between pin 7 (OSC) and V+ will lower the

oscillator frequency to 1kHz from its nominal frequency of 10kHz

(a multiple of 10), and thereby necessitate a corresponding

1

(5

1

(5



[

1

n (number of devices)

1

2

3

4

8

7

6

5

+

-

10

F

ICL7660

V+

+

-

10

F

V+

CMOS

GATE

1k



ICL7660A

FIGURE 17. EXTERNAL CLOCKING